Samsung revealed new memory architecture for AI chips

Samsung Electronics presented a conceptual zHBM architecture, in which high-speed memory is placed directly over the AI processor. The development was demonstrated at the Future of Memory and Storage 2026 exhibition in California.

In modern AI accelerators, HBM stacks are usually placed next to the GPU or specialized processor on a common substrate. In the zHBM system, the memory and computing chip are to be vertically integrated along the Z-axis.

This design shortens the data transfer path between the memory and the processor. It should increase bandwidth, reduce latency, and lower energy consumption when running large AI models.

According to Samsung's preliminary estimates, zHBM can deliver approximately four times the bandwidth of HBM4. The targeted energy consumption level is about a quarter of that of HBM4-based systems.

To manufacture such memory, the company plans to use a wafer-to-wafer multi-stack bonding technology. It is expected to provide tens of thousands of data exchange channels between the memory and the compute unit.

Samsung also showed the zNAND-O concept—a new NAND memory architecture aimed at AI systems. Both developments are presented only as conceptual models for now, and the company did not disclose timelines for their mass production.

At the same time, Samsung is expanding production of conventional high-speed memory. In 2026, the company began commercial shipments of HBM4 and delivered the first HBM4E samples to major customers.

Based on materials from: The Korea Herald, Seoul Economic Daily, Samsung Electronics